CS501 Advance Computer Architecture Assignment 2 Spring 2026

CS501 Advance Computer Architecture Assignment 2 Spring 2026.CS501 Advance Computer Architecture Assignment 2 Spring 2026. Assignment 2: Advanced Computer Architecture (CS501) – Spring 2026

CS501 Advance Computer Architecture Assignment 2 Spring 2026

Introduction

This assignment focuses on evaluating system performance through two critical metrics: I/O Bound Task Analysis and Bus Performance Metrics (IOPS). Understanding these concepts is essential for analyzing how hardware architecture impacts overall system efficiency.

Part 1: CPU Performance and I/O Activity Analysis

In a computer system, the total execution time (Elapsed Time) is divided between CPU processing and I/O activities. High I/O time often indicates that a system is “I/O bound,” meaning the processor remains idle while waiting for data transfers.

Calculation Methodology

• I/O Time (Sec): Calculated as Elapsed Time - CPU Time.
• Percentage of Elapsed Time: Calculated as (I/O Time / Elapsed Time) * 100.

Performance Data Table

Elapsed Time (Sec)	CPU Time (Sec)	I/O Time (Sec)	I/O Percentage (%)
500	410	90	18.00%
313	230	83	26.52%
426	300	126	29.58%
219	192	27	12.33%
141	72	69	48.94%

Part 2: Bus Performance and IOPS Determination

Input/Output Operations Per Second (IOPS) is a standard measure of bus performance. It is heavily influenced by the overhead of bus requests and arbitration.

Calculation Methodology

• Formula: Maximum IOPS (Million) = 1,000 / Average Time to Complete Operation (ns).
• Criterion: A system successfully meets the 40 million IOPS requirement if the calculated value is $\geq 40$.

Bus Performance Table

Bus Request (ns)	Arbitration (ns)	Avg Time (ns)	Max IOPS (Million)	40 Million IOPS?
6	7	10	100.00	Yes
9	10	12	83.33	Yes
14	8	11	90.91	Yes
5	8	11	90.91	Yes
12	13	10	100.00	Yes

Conclusion

The analysis reveals that system throughput is inversely proportional to the average time required for operation completion. To maintain high IOPS, designers must prioritize reducing the arbitration and bus request latency in the architectural design.